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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011, 2012. all rights reserved intersil (and design) and femtocharge are trademarks owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. dual 14-bit, 250/200/125 msps jesd204b high speed serial output adc isla224s the isla224s is a series of low-power, high-performance, dual-channel 14-bit, analog-to-digital converters. designed with femtocharge? technology on a standard cmos process, the series supports sampling rates of up to 250msps. the isla224s is part of a pin-compatible family of 12- and 14-bit dual-channel a/ds with maximum sample rates ranging from 125msps to 250msps and shares the same analog core as intersil's proven isla224p series of adcs. the family minimizes power consumption while providing state-of-the art dynamic performance, offering an optimal performance-vs- power trade-off. differentiating the isla224s from the isla224p is its highly configurable, jesd204b-compliant, high speed serial output link. the link offers data rates up to 4.375gbps per lane and multiple packing modes. it can be configured to use two or three lanes to transmit the conversion data, allowing for flexibility in the receiver design. the serdes transmitter also provides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements. a serial peripheral interface (spi) port allows for extensive configurability of the jesd204b transmitter including access to its built-in link and transport-layer test patterns. the spi port also provides control for nu merous additional features including the fine gain and offset adjustments of the two adc cores as well as the programmab le clock divider, enabling 2x and 4x harmonic clocking. the isla224s is available in a space-saving 7mmx7mm 48 ld qfn package. the package features a thermal pad for improved thermal performance and is specified over the full industrial temperature range (-40c to +85c). features ?jesd204a/b high speed data interface -jesd204a compliant - jesd204b device subclass 0 compliant - jesd204b device subclass 2 compatible - up to 3 jesd204 output lanes running up to 4.375gbps - highly configurable jesd204 transmitter ? multiple chip time alignment and deterministic latency support (jesd204b device subclass 2) ? spi programmable debugging features and test patterns ? 48-pin qfn 7mmx7mm package key specifications ? snr @ 250/200/125msps 73.2/74.1/75.1 dbfs f in = 30mhz 72.4/72.9/73.2 dbfs f in = 190mhz ? sfdr @ 250/200/125msps 82/91/94 dbc f in = 30mhz 84/82/81 dbc f in = 190mhz ? total power consumption: 989mw @ 250msps applications ? radar and satellite antenna array processing ? broadband communications and microwave receivers ? high-performance data acquisition ? communications test equipment ? high-speed medical imaging figure 1. serdes data eye at 4.375gbps pin-compatible family model resolution speed (msps) product availability isla224s25 14 250 now isla224s20 14 200 now isla224s12 14 125 now isla222s25 12 250 now isla222s20 12 200 now isla222s12 12 125 now may 7, 2012 fn7911.1
isla224s 2 fn7911.1 may 7, 2012 pin configuration isla224s (48 ld qfn) top view figure 2. block diagram jesd204 transmitter sha 1.25v ainp ainn 14-bit 250msps adc sha binp binn 14-bit 250msps adc vref clkp clkn spi control csb sclk sdio vref ovss avss avdd ovdd sync napslp sdo + ? resetn vcm clock generation lane[2:0]p lane[2:0]n avss (pll) ovdd (pll) dnc avdd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 clkdiv sdio ovss ovdd resetn avdd avdd clkp clkn syncp ovss (pll) ovdd (pll) syncn dnc lane1p lane1n ovss lane0n lane0p ovss lane2p lane2n vcm avdd avss binp binn avss avss ainn ainp avss dnc avdd ovss (pll) ovdd (pll) ovdd ovss ovss ovdd ovss csb sclk dnc pad ? exposed paddle sdo napslp
isla224s 3 fn7911.1 may 7, 2012 pin descriptions pin number name function 2, 11, 14, 15, 46 avdd 1.8v analog supply 12, 20, 47, 48 dnc do not connect 3, 6, 7, 10 avss analog ground 4, 5 binp, binn b-channel analog input positive, negative 8, 9 ainn, ainp a-channel analog input negative, positive 1 vcm common mode output 44 clkdiv clock divider control 16, 17 clkp, clkn clock input true, complement 45 napslp power control (nap, sleep modes) 13 resetn power on reset (active low) 26, 29, 32, 35, 37, 38 ovss output ground 25, 36, 39 ovdd 1.8v digital supply 22, 24 ovdd (pll) 1.8v analog supply for serdes pll 21, 23 ovss (pll) analog ground supply for serdes pll 18, 19 syncp, syncn jesd204 sync input 27, 28 lane0p, lane0n serdes lane 0 30, 31 lane1p, lane1n serdes lane 1 33, 34 lane2p, lane2n serdes lane 2 40 sdo spi serial data output 41 csb spi chip select (active low) 42 sclk spi clock 43 sdio spi serial data input/output pad avss exposed paddle. analog ground (connect to avss) ordering information part number (notes 1, 2) part marking temp. range (c) package (pb-free) pkg. dwg. # isla224s25ir1z isla224s25 ir1z -40 to +85 48 ld qfn l48.7x7g isla224s20ir1z isla224s20 ir1z -40 to +85 48 ld qfn l48.7x7g isla224s12ir1z isla224s12 ir1z -40 to +85 48 ld qfn l48.7x7g coming soon ISLA224S25IR48EV1Z fmc based evaluation board (suppo rts 125/200/250 speed grades), inte rfaces with adcmb-hsfmc-ev1z motherboard and other fpga vendor fmc based evaluation platforms coming soon adcmb-hsfmc-ev1z fmc based motherboard notes: 1. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate-e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free pr oducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 2. for moisture sensitivity level (msl), please see device information page for isla224s12 , isla224s20 , isla224s25 . for more information on msl please see techbrief tb363 .
isla224s 4 fn7911.1 may 7, 2012 table of contents key specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . 5 digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 switching specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . 10 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-on calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 user initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 temperature calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nap/sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 clock divider synchronous reset . . . . . . . . . . . . . . . . . . . . 20 soft reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 jesd204 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 initial lane alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . 25 spi physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 device configuration/control . . . . . . . . . . . . . . . . . . . . . . . . . 26 global device configuration/control . . . . . . . . . . . . . . . . . . 27 address 0xdf - 0xf3: jesd204 registers. . . . . . . . . . . . 28 address 0xdf-0xee: jesd204 parameter interface. . . . . 28 spi memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 adc evaluation platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 split ground and power planes . . . . . . . . . . . . . . . . . . . . . . . 36 clock input considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 exposed paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 bypass and filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 cml outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 unused inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
isla224s 5 fn7911.1 may 7, 2012 absolute maximum rating s thermal information avdd to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v ovdd to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4v to 2.1v avss to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v analog inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v clock inputs to avss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to avdd + 0.3v logic input to avss . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v logic inputs to ovss . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to ovdd + 0.3v latchup (tested per jesd-78c;class 2,level a) . . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 48 ld qfn (notes 3, 4, 5) . . . . . . . . . . . . . . 24 0.4 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c notes: 3. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 4. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 5. for solder stencil layout and reflow guidelines, please see tech brief tb389 . caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -2dbfs, f sample = maximum conversion rate (per speed grade). boldface limits apply over the operating temperature range, -40c to +85c. parameter symbol conditions isla224s25 isla224s20 isla224s12 units min (note 6) typ max (note 6) min (note 6) typ max (note 6) min (note 6) typ max (note 6) dc specifications analog input full-scale analog input range v fs differential 1.95 2.00 2.15 1.95 2.0 2.15 1.9 2.0 2.1 v p-p input resistance r in differential 600 600 600 input capacitance c in differential 7.4 7.4 7.4 pf full scale range temp. drift a vtc full temp 115 58 58 ppm/c input offset voltage v os -5.0 1 5.0 -5.0 1 5.0 -5.0 1 5.0 mv gain error e g 111% common-mode output voltage v cm 0.94 0.94 0.94 v common mode input current (per pin) i cm 6.0 6.0 6.0 a/msps clock inputs inputs common mode voltage 0.9 0.9 0.9 v clkp, clkn swing 1.8 1.8 1.8 v power requirements 1.8v analog supply voltage avdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v digital supply voltage ovdd 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v 1.8v analog supply current i avdd 353 375 324 344 282 316 ma 1.8v digital supply current i ovdd minimum number of lanes active 195 213 179 196 123 173 ma
isla224s 6 fn7911.1 may 7, 2012 power supply rejection ratio (note 7) psrr 30mhz 200mvp-p 40 40 40 db 1mhz 200mvp-p 47 47 47 db total power dissipation normal mode p d 989 1058 910 972 731 843 mw nap mode p d 447 490 391 453 290 398 mw sleep mode p d csb at logic high 5 12 5 12 6 12 mw nap mode wakeup time sample clock running 555s sleep mode wakeup time sample clock running 111ms ac specifications (note 8) differential nonlinearity dnl f in =105mhz no missing codes -1.0 0.4 1.5 -0.5 0.2 1 -1.0 0.18 lsb integral nonlinearity inl 3.0 2.0 2.0 lsb minimum conversion rate (note 9) f s min isla224s25/20 (3 lanes, efficient packing) isla224s12 (2 lanes, simple packing) 100 100 50 msps maximum conversion rate (note 9) f s max efficient packing 250 200 125 msps simple packing 155 125 msps minimum serdes lane data rate independent of packing mode 1.0 1.0 1.0 gbps maximum serdes lane data rate (see ?lane data rate? on page 22.) independent of packing mode 4.375 4.375 4.375 gbps signal-to-noise ratio (note 10) snr f in = 30mhz 73.1 73.8 75.1 dbfs f in = 105mhz 70.8 72.9 72.5 73.6 73.0 74.4 dbfs f in = 190mhz 72.4 72.9 73.2 dbfs f in = 363mhz 71.1 71.1 70.6 dbfs f in = 495mhz 70.0 69.5 68.8 dbfs f in = 605mhz 69.0 68.3 67.3 dbfs signal-to-noise and distortion (note 10) sinad f in = 30mhz 72.9 73.7 74.8 dbfs f in = 105mhz 68.8 72.5 72.0 73.4 72.7 74.1 dbfs f in = 190mhz 72.1 72.1 72.4 dbfs f in = 363mhz 70.1 70.3 67.5 dbfs f in = 495mhz 66.5 65.8 62.8 dbfs f in = 605mhz 58.8 58.5 54.7 dbfs electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -2dbfs, f sample = maximum conversion rate (per speed grade). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions isla224s25 isla224s20 isla224s12 units min (note 6) typ max (note 6) min (note 6) typ max (note 6) min (note 6) typ max (note 6)
isla224s 7 fn7911.1 may 7, 2012 effective number of bits (note 10) enob f in = 30mhz 11.72 11.94 12.14 bits f in = 105mhz 11.14 11.22 11.67 11.80 11.78 11.91 bits f in = 190mhz 11.54 11.63 11.68 bits f in = 363mhz 11.22 11.26 10.63 bits f in = 495mhz 10.43 10.33 9.79 bits f in = 605mhz 9.13 9.04 8.62 bits spurious-free dynamic range (note 10) sfdr f in = 30mhz 86 89 94 dbc f in = 105mhz 74 85 76 88 76 86 dbc f in = 190mhz 84 82 81 dbc f in = 363mhz 78 79 69 dbc f in = 495mhz 68 67 62 dbc f in = 605mhz 58 57 53 dbc spurious-free dynamic range excluding h2, h3 (note 10) sfdrx23 f in = 30mhz 87 90 96 dbc f in = 105mhz 89 92 94 dbc f in = 190mhz 89 91 92 dbc f in = 363mhz 86 88 87 dbc f in = 495mhz 86 84 84 dbc f in = 605mhz 85 83 82 dbc intermodulation distortion imd f in = 70mhz 83 83 83 dbfs f in = 170mhz 97 95 95 dbfs channel-to-channel isolation f in = 10mhz 88 90 100 db f in = 124mhz 82 87 86 db word error rate wer 10 -13 10 -13 10 -13 full power bandwidth fpbw 675 675 675 mhz notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. psrr is calculated by the equation 20*log10(a/b), where b is th e amplitude of a disturber sinuso id on avdd at the device pins , and a is the amplitude of the spur in the captured data at the frequency of the disturber sinusoid. 8. ac specifications apply after internal calibration of the adc is invoked at the given sample rate and temperature. refer to ? power-on calibration? on page 15 and ?user initiated reset? on page 16 for more detail. 9. the dll range setting must be changed via spi for adc core sa mple rates below 80msps. the jesd204 transmitter can support adc sample rates below 100msps, as long as the serdes lane data rate is greater than or equal to 1gbps. 10. minimum specification guaran teed when calibrated at +85c. electrical specifications all specifications apply under the following conditions unless otherwise noted: avdd = 1.8v, ovdd = 1.8v, t a = -40c to +85c (typical specifications at +25c), a in = -2dbfs, f sample = maximum conversion rate (per speed grade). boldface limits apply over the operating temperature range, -40c to +85c. (continued) parameter symbol conditions isla224s25 isla224s20 isla224s12 units min (note 6) typ max (note 6) min (note 6) typ max (note 6) min (note 6) typ max (note 6)
isla224s 8 fn7911.1 may 7, 2012 digital specifications boldface limits apply over the operat ing temperature range, -40c to +85c. parameter symbol conditions min (note 6) typ max (note 6) units cmos inputs input current high (resetn) i ih v in = 1.8v 1 10 a input current low (resetn) i il v in = 0v -25 -12 -7 a input current high (sdio, scl, sda sclk) i ih v in = 1.8v 4 12 a input current low (sdio, scl, sda sclk) i il v in = 0v -600 -400 -300 a input current high (csb) i ih v in = 1.8v 40 52 70 a input current low (csb) i il v in = 0v 1 10 a input voltage high (sdio, resetn) v ih 1.17 v input voltage low (sdio, resetn) v il 0.63 v input current high (napslp, clkdiv) (note 11) i ih 19 25 30 a input current low (napslp, clkdiv) i il --30 -25 -19 a input capacitance c di 4pf lvds inputs (syncp, syncn) input common mode range v icm 825 1575 mv input differential swing (peak-to-peak, single-ended) v id 250 450 mv input pull-up and pull-down resistance r ipu 100 k ? cml outputs output common mode voltage 1.14 v switching specifications boldface limits ap ply over the operating temperature range, -40c to +85c. parameter symbol condition min (note 6) typ max (note 6) units adc output aperture delay t a 190 ps rms aperture jitter j a 100 fs synchronous clock divider reset recovery time (note 12) t rstrt dll recovery time after synchronous reset 250 s latency (adc pipeline delay) l 10 cycles overvoltage recovery t ovr 1cycles serdes pll lock time 250 s pll bandwidth 2.2 mhz added random jitter 5ps rms added deterministic jitter 7ps p-p maximum input sample clock total jitter to maintain serdes ber <1e-12 integrated from 1khz to 10mhz offset from carrier 5ps rms
isla224s 9 fn7911.1 may 7, 2012 lvds inputs syncp, syncn setup time (with respect to the positive edge of clkp) t rsts avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c 400 75 ps syncp, syncn hold time (with respect to the positive edge of clkp) t rsth avdd, ovdd = 1.7v to 1.9v, t a = -40c to +85c 150 350 ps cml outputs output rise time t r 165 ps output fall time t f 145 ps data output duty cycle 50 % differential output resistance 100 ? differential output voltage (note 13) 760 mv p-p spi interface (notes 14, 15) sclk period t clk write operation 7 cycles t clk read operation 16 cycles csb to sclk setup time t s read or write 2 cycles csb after sclk hold time t h read or write 5 cycles data valid to sclk setup time t ds read or write 6 cycles data valid after sclk hold time t dh read or write 4 cycles data valid after sclk time t dvr read 4 cycles notes: 11. the tri-level inputs internal switching thresholds are approx imately. 0.43v and 1.34v. it is advised to float the inputs, ti e to ground or avdd depending on desired function. 12. the synchronous clock divider reset function is available as a (spi-programmable) overload on the sync input. 13. the voltage is expressed in peak-to-peak differential swing. the peak-to-peak sing le-ended swing is 1/2 of the differential swing. 14. the spi interface timing is directly proportional to the adc sample period (t s ). values above reflect multiples of a 4ns sample period, and must be scaled proportionally for lower sample rates. adc sample clock must be running for spi communication. 15. the spi may operate asynchronously with respect to the adc sample clock. switching specifications boldface limits ap ply over the operating temperature range, -40c to +85c. (continued) parameter symbol condition min (note 6) typ max (note 6) units
isla224s 10 fn7911.1 may 7, 2012 typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. figure 3. snr and sfdr vs f in figure 4. hd2 and hd3 vs f in figure 5. snr and sfdr vs a in (250msps) figure 6. hd2 and hd3 vs a in (250msps) figure 7. snr and sfdr vs f sample figure 8. hd2 and hd3 vs f sample 50 55 60 65 70 75 80 85 90 95 0 100 200 300 400 500 600 700 input frequency (mhz) snr (dbfs) and sfdr (dbc) sfdr at 200 msps sfdr at 250 msps sfdr at 125 msps snr at 250 msps snr at 200 msps snr at 125 msps -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 0 100 200 300 400 500 600 700 input frequency (mhz) hd2 and hd3 magnitude (dbc) hd2 at 200 msps hd2 at 250 msps hd2 at 125 msps hd3 at 250 msps hd3 at 200 msps hd3 at 125 msps 0 10 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 input amplitude (dbfs) snr and sfdr snr (dbfs) sfdr (dbfs) sfdr (dbc) snr (dbc) -120 -100 -80 -60 -40 -20 0 -60-50-40-30-20-10 0 hd2 and hd3 magnitude (dbc) input amplitude (dbfs) hd2 (dbc) hd3 (dbfs) hd2 (dbfs) hd3 (dbc) 60 65 70 75 80 85 90 50 100 150 200 250 300 snr (dbfs) and sfdr (dbc) sample rate (msps) sfdr snr -100 -95 -90 -85 -80 -75 50 100 150 200 250 300 hd2 and hd3 magnitude (dbc) sample rate (msps) hd2 hd3
isla224s 11 fn7911.1 may 7, 2012 figure 9. power vs f sample figure 10. differential nonlinearity (250msps) figure 11. integral nonlinearity (250msps ) figure 12. snr and sfdr vs vcm (250msps) figure 13. differential nonlinearity (125msps) figure 14. integral nonlinearity (125msps) typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. (continued) 0 200 400 600 800 1000 1200 50 100 150 200 250 300 total power (mw) sample rate (msps) 3 lanes 2 lanes efficient packing -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 5000 10000 15000 code dnl (lsbs) -4 -3 -2 -1 0 1 2 3 4 0 5000 10000 15000 code inl (lsbs) 60 65 70 75 80 85 90 700 800 900 1000 1100 1200 1300 1400 1500 vcm (mv) snr (dbfs) and sfdr (dbc) sfdr snr -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 5000 10000 15000 code dnl (lsbs) -4 -3 -2 -1 0 1 2 3 4 0 5000 10000 15000 code inl (lsbs)
isla224s 12 fn7911.1 may 7, 2012 figure 15. noise histogram (250msps) figure 16. single-tone sp ectrum @ 105mhz (250msps) figure 17. single-tone sp ectrum @ 190mhz (250msps) figure 18. single-tone spectrum @ 363mhz (250msps) figure 19. noise spectrum (125msps) figure 20. single-tone spec trum at 105mhz (125msps) typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. (continued) 01 43 514 2765 9571 4650 1118 146 11 0 0 2000 4000 6000 8000 10000 12000 14000 adc code number of hits 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 11181 stdev = 1.07 codes -120 -100 -80 -60 -40 -20 0 0 20406080100120 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 72.8 dbfs sfdr = 83 dbc sinad = 72.2 dbfs -120 -100 -80 -60 -40 -20 0 0 20406080100120 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 71.9 dbfs sfdr = 80 dbc sinad = 71.1 dbfs -120 -100 -80 -60 -40 -20 0 0 20406080100120 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 70.5 dbfs sfdr = 74 dbc sinad = 68.8 dbfs 0 2 94 74 0 0 0 5000 10000 15000 code number of hits std ev = 0.95 13176 8157 8451 1360 1454 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 74.8 dbfs sfdr = 87.1 dbc sinad = 74.7 dbfs
isla224s 13 fn7911.1 may 7, 2012 figure 21. single-tone spectrum at 190mhz (125msps) figure 22. single-tone at 363mhz (125msps) figure 23. two-tone spectrum (f1 = 70mhz, f2 = 71mhz at -7dbfs) (250msps) figure 24. two-tone spectrum (f1 = 170mhz, f2 = 171mhz at - 7dbfs) (250msps) figure 25. serdes data eye at 1.0gbps figure 26. serdes data eye at 3.0gbps typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. (continued) 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 73.7 dbfs sfdr = 86.8 dbc sinad = 73.4 dbfs 0 10 20 30 40 50 60 -120 -100 -80 -60 -40 -20 0 frequency (mhz) amplitude (dbfs) a in = -2.0 dbfs snr = 70.8 dbfs sfdr = 71.2 dbc sinad = 68.8 dbfs -120 -100 -80 -60 -40 -20 0 050100 frequency (mhz) magnitude (dbfs) imd = -82 dbfs -120 -100 -80 -60 -40 -20 0 050100 frequency (mhz) magnitude (dbfs) imd = -92 dbfs
isla224s 14 fn7911.1 may 7, 2012 figure 27. serdes data eye at 4.375gbps figure 28. serdes bathtub at 1.0gbps figure 29. serdes bathtub at 3.0gbps figure 30. serdes bathtub at 4.375gbps figure 31. serdes histogram at 1.0gbps figure 32. serdes histogram at 3.0gbps typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. (continued)
isla224s 15 fn7911.1 may 7, 2012 theory of operation functional description the isla224s is based upon a 14-bit, 250msps adc converter core that utilizes a pipelined successive approximation architecture (see figure 34). the input voltage is captured by a sample-hold amplifier (sha) and converted to a unit of charge. proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. decisions made during the successive appr oximation operations determine the digital code for each input valu e. digital error correction is also applied. power-on calibration the adc core(s) perform a self-calib ration at start-up. an internal power-on-reset (por) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a th reshold. the following conditions must be adhered to for the power-on calibration to execute successfully: ? a frequency-stable conversion clock must be applied to the clkp/clkn pins ? dnc pins must not be connected ? sdo has an internal pull-up and should not be driven externally ? resetn is pulled low by the adc internally during por. external driving of resetn is optional. ? spi communications must not be attempted during calibration, with the only ex ception of performing read operations on the cal_done register at address 0xb6. a user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. after the power supply has stabilized, the internal por releases resetn and an internal pull-up pulls it high, which starts the calibration sequence. if a subseq uent user-initiated reset is desired, the resetn pin should be connected to an open-drain driver with an off-state/high impedance state leakage of less than 0.5ma to assure exit from the reset state so calibration can start. the calibration sequence is initiated on the rising edge of resetn, as shown in figure 35. calibration status can be determined by reading the cal_status bit (lsb) at 0xb6. this bit is ?0? during calibration and goes to a logic ?1? when calibration is complete. during calibration the jesd204 transmitter pll is not locked to the adc sample clock, so the cml outputs will toggle at an undetermined rate. normal operation is resumed once calibration is complete. at 250msps the nominal calibrati on time is 280ms, while the maximum calibration time is 550ms. figure 33. serdes histogram at 4.375gbps typical performance curves all typical performance characteristics apply under the followin g conditions unless otherwise noted: avdd = ovdd = 1.8v, t a = +25c, a in = -2dbfs, f in = 105mhz, f sample = 250msps. (continued)
isla224s 16 fn7911.1 may 7, 2012 user initiated reset recalibration of the adc can be in itiated at any time by driving the resetn pin low for a minimum of one clock cycle. an open-drain driver with a drive strength in its high impedance state of less than 0.5ma is re commended, as resetn has an internal high impedance pull-up to ovdd. as is the case during power-on reset, resetn and dnc pins must be in the proper state for the calibration to successfully execute. the performance of the isla224s changes with variations in temperature, supply voltage or sample rate. the extent of these changes may necessitate recalibr ation, depending on system performance requirements. best performance will be achieved by recalibrating the adc under th e environmental conditions at which it will operate. a supply voltage variation of <100mv will generally result in an snr change of <0.5d bfs and sfdr change of <3dbc. in situations where the sample rate is not constant, best results will be obtained if the device is calib rated at the highest sample rate. reducing the sample rate by le ss than 80msps will typically result in an snr change of <0 .5dbfs and an sfdr change of <3dbc. figures 36 through 41 show the affect of temperature on snr and sfdr performance with power on calibration performed at -40c, +25c, and +85c. each plot shows the variation of snr/sfdr across temperature after a single power on calibration at -40c, +25c an d +85c. best performance is typically achieved by a user-initi ated power on ca libration at the operating conditions, as stated earlier. however, it can be seen that performance drift with temp erature is not a very strong function of the temperature at wh ich the power on calibration is performed. figure 34. adc core block diagram digital error correction sha 1.25v inp inn clock generation 2.5- bit flash 6- stage 1.5- bit/ stage 3- stage 1-bit/ stage 3- bit flash + ? flash 2.5-bit figure 35. calibration timing clkp clkn calibration begins calibration complete calibration time resetn cal_status bit
isla224s 17 fn7911.1 may 7, 2012 temperature calibration figure 36. typical snr perf ormance vs temperature, device calibrated at -40 c , f in = 105mhz figure 37. typical sfdr pe rformance vs temperature, device calibrated at -40 c , f in = 105mhz figure 38. typical snr perf ormance vs temperature, device calibrated at +25 c , f in = 105mhz figure 39. typical sfdr performance vs temperature, device calibrated at +25 c , f in = 105mhz figure 40. typical snr perf ormance vs temperature, device calibrated at +85 c , f in = 105mhz figure 41. typical sfdr performance vs temperature, device calibrated at +85 c , f in = 105mhz 71 72 73 74 75 76 -40 -35 -30 -25 -20 temperature (c) snr (dbfs) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps 75 80 85 90 -40 -35 -30 -25 -20 temperature (c) sfdr (dbc) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps 71 72 73 74 75 76 5 1015202530354045 temperature (c) snr (dbfs) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps 75 80 85 90 5 1015202530354045 temperature (c) sfdr (dbc) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps 68 69 70 71 72 73 74 75 76 65 70 75 80 85 temperature (c) snr (dbfs) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps 75 80 85 90 65 70 75 80 85 temperature (c) sfdr (dbc) -1dbfs, 125msps -2dbfs, 125msps -1dbfs, 200msps -2dbfs, 200msps -1dbfs, 250msps -2dbfs, 250msps
isla224s 18 fn7911.1 may 7, 2012 analog input a single fully differential inpu t (vinp/vinn) connects to the sample and hold amplifier (sha) of each unit adc. the ideal full-scale input voltage is 2.0v, centered at the vcm voltage as shown in figure 42. best performance is obtained when the analog inputs are driven differentially. the common-mode ou tput voltage, vcm, should be used to properly bias the inputs as shown in figures 43 through 45. an rf transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (if) inputs. two different transformer input schemes are shown in figures 43 and 44. this dual transformer scheme is used to improve common-mode rejection, which keeps the co mmon-mode level of the input matched to vcm. the value of the shunt resistor should be determined based on the desired load impedance. the differential input resistance of the isla224s is 600 . the sha design uses a switched capacitor input stage (see figure 58), which creates current spikes when the sampling capacitance is reconnected to the input voltage. this causes a disturbance at the input, which must settle before the next sampling point. lower source impedance will result in faster settling and improved performance. therefore a 2:1 or 1:1 transformer and low shunt resi stance are recommended for optimal performance. a differential amplifier, as show n in the simplified block diagram in figure 45, can be used in applications that require dc-coupling. in this configuratio n, the amplifier will typically dominate the achievable snr and distortion performance. intersil?s new isl552xx differential amplifier family can also be used in certain ac applications with minimal performance degradation. contac t the factory for more information. when an over range occurs, the data sample output bits are held at full scale (all 0?s or all 1?s), th us allowing the detection of this condition in the receiver device. clock input the clock input circuit is a differential pair (see figure 59). driving these inputs with a high level (up to 1.8v p-p on each input) sine or square wave will provide the lowest jitter performance. a transformer with 4:1 impedance ratio will provide increased drive levels. the clock input is functional with ac-coupled lvds, lvpecl, and cml drive levels. to maintain the lowest possible aperture jitter, it is recommended to have high slew rate at the zero crossing of the differential clock input signal. the recommended drive circuit is shown in figure 46. a duty range of 40% to 60% is acceptable. the clock can be driven single-ended, but this will reduce the edge rate and may impact snr performance. the clock inputs are internally self-biased to av dd /2 through a thevenin equivalent of 10k to facilitate ac coupling. a selectable 2x or 4x frequency divider is provided in series with the clock input. the divider can be used in the 2x mode with a sample clock equal to twice the desired sample rate or in 4x mode with a sample clock equal to four times th e desired sample rate. use of the 2x or 4x frequency divi der enables the use of the phase slip feature, which enables the system to be able to select the phase of the figure 42. analog input range 1.0 1.8 0.6 0.2 1.4 vinp vinn vcm 1.0v figure 43. transformer input for general purpose applications adt1-1wt 0.1f adc vcm adt1-1wt 1000pf figure 44. transmission-line transformer input for high if applications adc vcm 1000pf 1000pf tx-2-5-1 adtl1-12 figure 45. differential amplifier input adc figure 46. recommended clock drive tc4-19g2+ 1000pf 1000pf clkp clkn 0.01f 200 1000pf
isla224s 19 fn7911.1 may 7, 2012 divide by 2 or divide by 4 that causes the adc to sample the analog input. the clock divider can also be controlled through the spi port, which overrides the clkdiv pin setting. see ?spi physical interface? on page 25. a delay-locked loop (dll) generates internal clock signals for vari ous stages within the charge pipeline. if the frequency of the input clock changes, the dll may take up to 52 s to regain lock at 250m sps. the lock time is inversely proportional to the sample rate. the dll has two ranges of operation, slow and fast. the slow range can be used for adc core sample rates between 40msps and 100msps, while the default fast range can be used from 80msps to the maximum specified sample rate. the lane data rate is related to the adc core sample rate by a relationship that is defined by the jesd204 tran smitter configuration, and has additional frequency constraint s; see?jesd204 transmitter? on page 20 for additional details. jitter in a sampled data system, cloc k jitter directly impacts the achievable snr performance. the theoretical relationship between clock jitter (t j ) and snr is shown in equation 1 and is illustrated in figure 47. this relationship shows the snr that would be achieved if clock jitter were the only non-ideal factor. in reality, achievable snr is limited by internal factors such as linearity, aperture jitter and thermal noise as well. internal aper ture jitter is the uncertainty in the sampling instant. the internal aperture jitter combines with the input clock jitter in a root-s um-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. the total jitter, combined with other noise sources, then determines the achievable snr. voltage reference a temperature compensated internal voltage reference provides the reference charges used in the successive approximation operations. the full-scale range of each adc is proportional to the reference voltage. the nominal value of the voltage reference is 1.25v. digital outputs the digital outputs are in cml format, and feature analog and digital characteristics compliant with the jesd204 standard requirements. power dissipation the power dissipated by the device is dependent on the adc sample rate and the number of active lanes in the link. there is a fixed bias current drawn from the analog supply for the adc, along with a fixed bias current dr awn from the digital supply for each active lane. the remaining power dissipation is linearly related to the sample rate. nap/sleep portions of the device may be shut down to save power during times when operation of the adc is not required. two power saving modes are available: nap, and sleep. nap mode reduces power dissipation significantly while taking a very short time to return to functionality. sleep mode reduces power consumption drastically while taking longer to return to functionality. in nap mode the jesd204 lanes will continue to produce valid encoded data, allowing the link to re main active and thus return to a functional state quickly. the data transmitted over the lanes in nap mode is the last valid adc sample, repeated until leaving nap mode. the 8b/10b encoder?s runn ing disparity will prevent the potentially long time repetition of this last valid sample from creating dc bias on the lane. in sleep mode the jesd204 lanes will be deactivated to conserve power. thus, sometime after wake up code group alignment will be required to reestablish the link. the input clock should remain ru nning and at a fixed frequency during nap or sleep, and csb sh ould be high. the jesd204 link will only remain established during nap mode if the input clock continues to remain stable during the nap period. by default after the device is powered on, the operational state is controlled by the napslp pin as shown in table 2. please note that power on calibration occurs at power up time regardless of the state of the napslp pin; immediately following this power on calibration routine the device will enter nap or sleep state if the napslp pin voltage dictates it is to do so. the power-down mode can also be controlled through the spi port, which overrides the napslp pin setting. details on this are contained in ?serial peripher al interface? on page 25. table 1. clkdiv pin settings clkdiv pin divide ratio avss 2 float 1 avdd 4 snr 20 log 10 1 2 f in t j ------------------- - ?? ?? = (eq. 1) figure 47. snr vs clock jitter tj = 100ps tj = 10ps tj = 1ps tj = 0.1ps 10 bits 12 bits 14 bits 50 55 60 65 70 75 80 85 90 95 100 1m 10m 100m 1g snr (db) input frequency (hz) table 2. napslp pin settings napslp pin mode avss normal float nap avdd sleep
isla224s 20 fn7911.1 may 7, 2012 data format output data can be presented in three formats: two?s complement(default), gray code and offset binary. the data format can be controlled throug h the spi port by writing to address 0x73. details on this are contained in ?serial peripheral interface? on page 25. offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the mo st positive input to 0xfff (all ones). two?s complement coding simply complements the msb of the offset binary representation. when calculating gray code the msb is unchanged. the remaining bits are computed as the xor of the current bit position and the next most significant bit. figure 48 shows this operation. converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in figure 49. mapping of the input voltage to the various data formats is shown in table 3. . clock divider synchronous reset the function of clock divider sync hronous reset is available as a spi-programmable overloaded function on the syncp and syncn pins. given that the clock divider reset and sync features have the same electrical an d timing requirements, this overloading allows the system to generate only a single well timed signal with respect to the adc sample clock and select the adc?s interpretation of the signal as a spi-programmable option (see spi register 0x77 description for more information). by default the syncp and syncn pins will function as the jesd204 sync~. the use of clock divider reset function is a requirement in a system that uses the isla214s 50, isla214s35, or clkdiv = 2 or 4 and also requires time alignment or deterministic latency of multiple devices. please contac t the factory for more details about this feature and its usage. soft reset soft reset is a function intended to be used when the power on reset is to be re-run. an application may decide to issue a soft calibration command after significant temperature change or after a change in the sample rate frequency to optimize performance under the new condition. soft reset is issued by writing the soft reset bit at spi address 0x00. soft reset is a self-resetting bit in that will automatically return to 0 once the power on calibration has completed. jesd204 transmitter overview the conversion data is presented by a jesd204b-compliant serdes interface. the serdes lane data rate supports typical speeds up to 4.375gbps, exceeding the 3.125gbps maximum specified by the jesd204 rev a standard. two packing modes are supported: efficient and simple. a sync input is included, which is used for lane initialization as well as time alignment of multiple converter devices. ac coupling of the serdes lane(s) on the board is required. a block diagram of this serdes transmitter is shown in figure 50. for more information about the st andardized characteristics and features of a jesd204 interface, please see jesd204 rev a and rev b standards. for application design support, including evaluation kit schematics and layout, reference fpga project(s), and simulation models for functionality and signal integrity, please contact the factory and/or view application notes on the intersil website. figure 48. binary to gray code conversion 12 13 11 0 1 binary 12 13 11 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 figure 49. gray code to binary conversion 12 13 11 0 1 binary 12 13 11 0 gray code ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? table 3. input voltage to output code mapping input voltage offset binary two?s complement gray code ?full scale 00 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 ?full scale + 1lsb 00 0000 0000 0001 10 0000 0000 0001 00 0000 0000 0001 mid?scale 10 0000 0000 0000 00 0000 0000 0000 11 0000 0000 0000 +full scale ? 1lsb 11 1111 1111 1110 01 1111 1111 1110 10 0000 0000 0001 +full scale 11 1111 1111 1111 01 1111 1111 1111 10 0000 0000 0000
isla224s 21 fn7911.1 may 7, 2012 . to maximize flexibility at the system level, two transport layer packing modes are supported: simple and efficient. these two modes allow the system designer flexibility to trade off between the number of lanes to support a given throughput, the data rate of these lanes, and the complexity of the receiver. this translates directly into providing system level trade-offs between cost, power, and resource usage of the receiver and complexity of the solution. simple mode packs informationless bits onto each adc sample to form full 16-bit data. in simple mode packing, the frame clock and adc sample clock are the same frequency, easing frequency scaling requirements at the syst em level, but decreasing the payload efficiency of the lanes. decreased payload efficiency of the lanes increases the lane data rate required to support a given throughput, and may require additi onal lanes to support a given configuration. the degree of payload efficiency loss is dependent on the adc resolution. efficient mode packs sequential adc samples into a contiguous block of an integer number of octets, and then slices the block into the octets for transport. this mode always achieves the theoretical maximum payload of the lanes (80%) regardless of the resolution of the adc and the number of lanes used. this mode provides the minimum number of lanes at the minimum data rate that is theoretica lly possible given the 8b/10b encoding used in jesd204 systems. in efficient packing mode, frame clock and the adc sample clock have an m/n relationship, where m and n are small integers and vary depending on the adc resolution and number of lanes selected. efficient mode packing may require additional frequency scaling elements (internal fpga plls or discrete frequency scaling devices) to generate the frame clock for the receiving device. the default configuration for this device is efficient packing mode. reconfiguration into the simple packing mode is accomplished by programming the jesd204 parameters via the spi bus. see table 5 for the full list of parameters values for each mode and product. via spi, the jesd204 transmitter is highly configurable, supporting efficient to simple mode packing reconfiguration as well as ?d owngrading? a given product?s jesd204 interface. for example, reconfiguring a 3-lane product into 2 lanes (with each running faster than with 3 lanes), or reducing the resolution of the adc(s) to slow down the lane data rate in systems where the full adc resolution is not required, are supported. please contact intersil sales support for a full list of downgradeable configurations that are supported. signal integrity plots, including data eye, ber bathtub curves, and edge histogram plots versus lane data rate can be found in the ?typical performance curves? on page 10. initial lane alignment the link initialization process is started by asserting the sync~ signal to the adc device. this assertion causes the jesd204 transmitter to generate comma characters, which are used by the receiver to accomplish code group synchronization (bit and octet alignment, respectively). once code group synchronization is detected in the receiver, it de-a sserts the sync~ signal, causing the jesd204 transmitter to generate the initial lane alignment sequence (ila). the ila is comprise d of 4 multi-frames of data in a standard format, with the length of each multi-frame determined by the k parameter as programmed into the spi jesd204 parameter table. the ila includes standard control character markers that can be used to perform channel bonding in the receiving device if desired. the 2nd multi-frame incl udes the full jesd204 parameter figure 50. serdes transmitter block diagram sample clock sample data transport layer scrambler 1+x 14 +x 15 encoder 8/10 link layer sync pll multiply - code group synchronization - alignment characters - initial lane synchronization - etc ser logic lane 0 link layer serdes block lane 1 link layer lane 2 sample data analog input analog input clock management
isla224s 22 fn7911.1 may 7, 2012 data, allowing the receiver to auto-detect the lane configuration if desired. after completion of the ila the jesd204 transm itter begins transmitting adc sample data. continuous link and lane alignment monitoring is accompli shed via an octet substitution scheme. the last octet in each frame, if identical to the last octet in the previous frame, is replaced with a specific control character. if both sides of the link support lane synchronization, the last octet in each multi-frame, if identical to the last octet in the previous frame, is replaced with a different specific control character. a more complete descri ption of the link initialization sequence, including finite state machine implementation, can be found in the jesd204 rev a standard. lane data rate the lane data rate for this product family is a function of the adc sample rate, the number of serdes lanes used, and packing mode selected in the serdes transmitter. figure 51 illustrates the relationship between adc samp le rate and serdes lane rate for various transmitter configurations. the serdes can typically operate from lane rates of 1 to over 4.375gbs. for each adc speed grade, the serdes lanes are tested at its maximum adc sample rate using three lane efficient packing as well as two- lane, efficient packing for the 125msps speed version. lane data rate chart scrambler the bypassable scrambler is compliant with the scrambler defined in the jesd204 rev a standard. this implementation seeds the scrambler with the initial lane alignment sequence, such that the first two octets following the sequence can be properly descrambled if the receiver also passes the lane alignment sequen ce through its descrambler. even if the receiver does not im plement this detail, the 3rd and subsequent octets can be descrambled to yield adc data due to the self-synchronizing nature of the scrambler used. multi-chip time alignment the jesd204 standard (in various revisions) provides the capability to time a lign multiple jesd204 adc devices to a single logic device (fpga or asic). this feature is critical in many applications that cannot tolerate the variable latency of the jesd204 link, and that must process pipeline depth correct data from more than one adc device. time alignment of multiple devices provides the capability to align samples from multiple jesd204 adc devices in the system in a pipeline-depth correct manner , thus enabling the system to analyze the adc data from multip le devices while eliminating the variable latency of the jesd204 link as a concern. this capability enables configurations of je sd204 adcs as iq, interleave, and/or simultaneously-sampled converters. this adc family uses the asserted to de-asserted sync~ transition as the absolute time event with which to generate a known sequence of characters at the jesd204 transmitter of equal pipeline depth between all adc devices in the system to be time aligned. this is consistent with the jesd204 rev b subclass 2 device definition. test patterns the complexity of the jesd204 interface merits much more test pattern capability than less complex parallel interfaces. this device family consequently supports a much wider range of test patterns than previous adc families. supported test patterns include both transport and link layer patterns. transport layer patterns are passed through the transport layer of the jesd204 transmitter, following the same sequence of being packed and sliced into octets as the adc sample data. link layer test patterns bypass the transport layer and are injected directly into the 8b/10b encoder, serialized, and sent out of the physical media. test pattern generation is controlled through spi register 0xc0. link layer prbs patterns are standard prbs patterns that can be used with built-in standard prbs checkers in, for example, fpga serdes-capable pins. all transport layer test patterns re-initialize their phase when the sync~ de-assertion occurs; conseque ntly, a system that provides a well-timed sync~ signal with respect to the adc sample clock can expect transport layer test patterns to have consistent phase with respect to that de-assertion, which can be a significant aid when debugging the system. 1000 1500 2000 2500 3000 3500 4000 4500 50 70 90 110 130 150 170 190 210 230 250 adc sample rate (msps) figure 51. lane data rate as a function of packing and adc sample rate lane rate (mbps) 4.375 gbps 3.125 gbps (jesd204) 2 lanes (simple packing) 2 lanes (efficient packing) 3 lanes (efficient packing) 3 lanes (simple packing) table 4. jesd204 configuratio ns and clock frequencies adc sample clock range (mhz) lane data rate multiplier from adc sample clock rate lane data rate (gbps) 100-250 (efficient packing) 3 lanes (14-bits)*( 2 adc channels)*(10/8 encoder overhead)/(3 lanes) = (280/24) = 11.6667 1.16667 to 2.916675 57-250 (efficient packing) 2 lanes (14-bits)*(2 adc channels)*(10/8 encoder overhead)/(2 lanes) = (280/16) = 17.5 1.00 to 4.375
isla224s 23 fn7911.1 may 7, 2012 50-219(simple packing) 2 lanes (14-bits+2-bit tail)*(2 adc channels)*(10/8 encoder overhead)/(2 lanes) = (320/16) = 20 1.00 to 4.375 table 4. jesd204 configurations an d clock frequencies (continued) adc sample clock range (mhz) lane data rate multiplier from adc sample clock rate lane data rate (gbps) table 5. jesd204 parameters packing mode number of lanes jesd204 parameter encoded jesd204 parameters and frame map (notes 16, 17, 18) efficient 3 cf = 0 0 cs = 0 0 c0s0[13:6] c0s0[5:0] c0s1[11:4] c0s1[3:0] c0s2[9:2] c0s2[1:0] c0s3[7:0] f = 7 6 c0s1[13:12] c0s2[13:10] c0s3[13:8] hd = 0 0 l = 3 2 c0s4[13:6] c0s4[5:0] c0s5[11:4] c0s5[3:0] c1s0[9:2] c1s0[1:0] c1s1[7:0] m = 2 1 c0s5[13:12] c1s0[13:10] c1s1[13:8] n = 14 13 n' = 14 13 c1s2[13:6] c1s2[5:0] c1s3[11:4] c1s3[3:0] c1s4[9:2] c1s4[1:0] c1s5[7:0] s = 6 5 c1s3[13:12] c1s4[13:10] c1s5[13:8] k >= 3 >= 2 efficient 2 cf = 0 0 cs = 0 0 c0s0[13:6] c0s0[5:0] c0s1[11:4] c0s1[3:0] c0s2[9:2] c0s2[1:0] c0s3[7:0] f = 7 6 c0s1[13:12] c0s2[13:10] c0s3[13:8] hd = 0 0 l = 2 1 c1s0[13:6] c1s0[5:0] c1s1[11:4] c1s1[3:0] c1s2[9:2] c1s2[1:0] c1s3[7:0] m = 2 1 c1s1[13:12] c1s2[13:10] c1s3[13:8] n = 14 13 n' = 14 13 s = 4 3 k >= 3 >=2 simple 2 cf = 0 0 cs = 0 0 c0s0[13:6] c0s0[5:0] f = 2 1 tt hd = 0 0 l = 2 1 c1s0[13:6] c1s0[5:0] m = 2 1 tt n = 14 13 n' = 16 15 s = 1 0 k >= 9 >= 8 notes: 16. the jesd204 parameters are shown as their actual values, with the jesd204 encoded values (i.e., the values that are programm ed into the spi registers) in the next column over. typically values that must always be greater than 1 are encoded as value minus 1, and so on . 17. frame map format decoder: "cxsy[a:b]" = converter x, sample y, bits a through b. for example, "c0s0[13:6]" = converter 0, sa mple 0, bits 13 through 6, etc. "t" = tail bit (information-less bit packed in the transport layer mapping to form octets). 18. the topmost lane in the graphical frame map is lane0, fo llowed by lane1 and lane 2 (for 3-lane configurations).
isla224s 24 fn7911.1 may 7, 2012 figure 52. msb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a10 figure 53. lsb-first addressing csb sclk sdio r/w w1 w0 a12 a11 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a2 figure 54. spi write t s t hi t clk t lo r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t h t dhw t dsw spi write csb sclk sdio figure 55. spi read ( 3 wire mode ) (4 wire mode) w1 w 0 a12 a9 a2 a1 d7 d6 d3 d2 d1 d7 d3 d2 d1 d0 a0 writing a read command reading data d0 t h t dvr spi read t hi t clk t lo t dhw t dsw t s csb sclk sdio sdo a11 a10 r/w
isla224s 25 fn7911.1 may 7, 2012 serial peripheral interface a serial peripheral interface (spi) bus is used to facilitate configuration of the device and to optimize performance. the spi bus consists of chip select (csb), serial clock (sclk) serial data output (sdo), and serial data input/output (sdio). the maximum sclk rate is equal to the adc sample rate (f sample ) divided by 7 for write operations and f sample divided by 16 for reads. there is no minimum sclk rate. the following sections describe various registers that are used to configure the spi or adjust perfor mance or functional parameters. many registers in the available address space (0x00 to 0xff) are not defined in this document. additionally, within a defined register there may be certain bits or bit combinations that are reserved. undefined registers and undefined values within defined registers are reserved and should not be selected. setting any reserved register or value may produce indeterminate results. spi physical interface the serial clock pin (sclk) provid es synchronization for the data transfer. by default, all data is presented on the serial data input/output (sdio) pin in three-wire mode. the state of the sdio pin is set automatically in the communication protocol (described in the following). a dedicated serial data output pin (sdo) can be activated by setting 0x00[7] high to allow operation in four-wire mode. the spi port operates in a half duplex master/slave configuration, with the adc functi oning as a slave. multiple slave devices can interface to a single master in three-wire mode only, since the sdo output of an unad dressed device is asserted in four wire mode. the chip-select bar (csb) pin determines when a slave device is being addressed. multiple slav e devices can be written to concurrently, but only one slave device can be read from at a given time (again, only in three- wire mode). if multiple slave devices are selected for reading at the same time, the results will be indeterminate. the communication protocol begins with an instruction/address phase. the first rising sclk edge following a high-to-low transition on csb determines the beginning of the two-byte instruction/address command; sclk must be static low before the csb transition. data can be presented in msb-first order or lsb-first order. the default is msb-first, but this can be changed by setting 0x00[6] high. figure s 52 and 53 show the appropriate bit ordering for the msb-first and lsb-first modes, respectively. in msb-first mode, the address is incremented for multi-byte transfers, while in lsb-fi rst mode it?s decremented. in the default mode, the msb is r/w, which determines if the data is to be read (active high) or written. the next two bits, w1 and w0, determine the number of data bytes to be read or written (see table 6). the lower 13 bits contain the first address for the data transfer. this relationship is illustrated in figure 54, and timing values are given in ?switching specifications? on page 8. after the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the adc (based on the r/w bit status). the data transfer will continue as long as csb remains low and sclk is active. stalling of the csb pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. for transfers of four bytes or more, csb is allowed to stall in the middle of the instruction/address bytes or before the first data byte. if csb transitions to a high state after that point the state machine will reset and terminate the data transfer. figure 56. 2-byte transfer csb sclk sdio instruction/address data word 1 data word 2 csb stalling figure 57. n-byte transfer csb sclk sdio instruction/address data word 1 data word n last legal csb stalling table 6. byte transfer selection [w1:w0] bytes transferred 00 1 01 2 10 3 11 4 or more
isla224s 26 fn7911.1 may 7, 2012 figures 56 and 57 illustrate the timing relationships for 2-byte and n-byte transfers, respective ly. the operation for a 3-byte transfer can be inferred from these diagrams. spi configuration address 0x00: chip_port_config bit ordering and spi reset are contro lled by this register. bit order can be selected as msb to lsb (m sb first) or lsb to msb (lsb first) to accommodate various micro controllers. bit 7 sdo active bit 6 lsb first setting this bit high configures the spi to interpret serial data as arriving in lsb to msb order. bit 5 soft reset setting this bit high resets all spi registers to default values. bit 4 reserved this bit should always be set high. bits 3:0 these bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. address 0x02: burst_end if a series of sequential register s are to be set, burst mode can improve throughput by eliminating redundant addressing. the burst is ended by pulling the csb pin high. setting the burst_end address determines the end of the transfer. during a write operation, the user must be ca utious to transm it the correct number of bytes based on the starting and en ding addresses. bits 7:0 burst end address this register value determines the ending address of the burst data . device information address 0x08: chip_id address 0x09: chip_version the generic die identifier and a revision number, respectively, can be read from these two registers. device configuration/control a common spi map, which can ac commodate single-channel or multi-channel devices, is used for all intersil adc products. address 0x20: offset_coarse_corea address 0x21: offset_fine_corea the input offset of adc corea can be adjusted in fine and coarse steps. both adjustments are made via an 8-bit word as detailed in table 7. the data format is twos complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x20 and 0x21 to be used by the adc.(see description for 0xfe) address 0x22: ga in_coarse_corea address 0x23: gain_medium_corea address 0x24: gain_fine_corea gain of the adc core can be adjusted in coarse, medium and fine steps. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. (?0011? ? -4.2% and ?1100? ? +4.2%) it is recommended to use one of the coarse gain settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the registers at 0x0023 and 0x24. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x23 and 0x24 to be used by the adc.(see description for 0xfe). address 0x25: modes two distinct reduced power modes can be selected. by default, the tri-level napslp pin can sele ct normal operation, nap or table 7. offset adjustments corea coreb parameter 0x20[7:0] 0x26[7:0] coarse offset 0x21[7:0] 0x27[7:0] fine offset steps 255 255 ?full scale (0x00) -133lsb (-47mv) -5lsb (-1.75mv) mid?scale (0x80) 0.0lsb (0.0mv) 0.0lsb +full scale (0xff) +133lsb (+47mv) +5lsb (+1.75mv) nominal step size 1.04lsb (0.37mv) 0.04lsb (0.014mv) table 8. coarse gain adjustment 0x22[3:0] corea 0x26[3:0] coreb nominal coarse gain adjust (%) bit3 +2.8 bit2 +1.4 bit1 -2.8 bit0 -1.4 table 9. medium and fine gain adjustments corea coreb parameter 0x23[7:0] 0x29[7:0] medium gain 0x24[7:0] 0x2a[7:0] fine gain steps 256 256 ?full scale (0x00) -2% -0.20% mid?scale (0x80) 0.00% 0.00% +full scale (0xff) +2% +0.2% nominal step size 0.016% 0.0016%
isla224s 27 fn7911.1 may 7, 2012 sleep modes (refer to?nap/sleep? on page 19). this functionality can be overridden and controlled through the spi. this register is not changed by a soft reset. address 0x26: offset_coarse_coreb address 0x27: offset_fine_coreb the input offset of adc coreb can be adjusted in fine and coarse steps in the same way that offset for corea can be adjusted. both adjustments are made via an 8-bit word as detailed in table 7. the data format is two?s complement. the default value of each register will be the result of the self-calibration after initial power-up. if a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register. bit 0 in register 0xfe must be set high to enable updates written to 0x26 and 0x27 to be used by the adc.(see description for 0xfe) address 0x28: gain_coarse_coreb address 0x29: gain_medium_coreb address 0x2a: gain_fine_coreb gain of adc coreb can be adjusted in coarse, medium and fine steps in the same way that corea can be adjusted. coarse gain is a 4-bit adjustment while medium and fine are 8-bit. multiple coarse gain bits can be set for a total adjustment range of 4.2%. bit 0 in register 0xfe must be set high to enable updates written to 0x29 and 0x2a to be used by the adc.(see description for 0xfe) global device configuration/control address 0x71: phase_slip when using the clock_divide feature, the sample clock edge that the adc uses to sample the anal og input signal can be one of several different edges on the incoming higher frequency sample clock. for example, in clock_divide = 2 mode, every other incoming sample clock edge gets used by the adc to sample the analog input. the phase_slip feature allows the system to control which edge of the incoming samp le clock signals gets used to cause the sampling event, by ?slipping? the sampling event by one input clock period each time phase_slip is asserted. the clkdivrst feature can work in conjunction with phase_slip. after well-timed assertion of the clkdivrst signal (via overloading on the sync inputs), the sampling edge position with respect to the incoming clock rate will have been reset, allowing the system to ?slip? whatever desired number of incoming clock periods from a known state. address 0x72: clock_divide the adc has a selectable clock divi der that can be set to divide by two or one (no division). by default, the tri-level clkdiv pin selects the divisor this functi onality can be overridden and controlled through the spi, as shown in table 11. this register is not changed by a soft reset. address 0x73: output_mode_a the output_mode_a register controls the logical coding of the sample data. data can be coded in three possible formats: two?s complement(default), gray code or offset binary. see table 12. this register is not changed by a soft reset. address 0x74: output_mode_b bit 6 dll range this bit sets the dll operating range to fast (default) or slow. internal clock signals are generate d by a delay-locked loop (dll), which has a finite operating range. table 13 shows the allowable sample rate ranges for the slow and fast settings. address 0x77: sync_function bit 0 clkdivrst this bit controls the functionalit y of the syncp, syncn pins on this device. by default, this bit equals ?0?, which means that the functionality of the syncp, syncn pins is the jesd204 sync. setting this bit equal to ?1? modifies the functionality of the syncp, syncn pins to be clkdivrst, which is a synchronous divider reset on all internal dividers in the device. usage of this clkdivrst functionality is required to support multi-chip time alignment and deterministic latency for devices that use interleaved product configurations (isla214s50 and table 10. power-down control value 0x25[2:0] power down mode 000 pin control 001 normal operation 010 nap mode 100 sleep mode table 11. clock divider selection value 0x72[2:0] clock divider 000 pin control 001 divide by 1 010 divide by 2 100 divide by 4 other not allowed table 12. output format control value 0x73[2:0] output format 000 two?s complement (default) 010 gray code 100 offset binary table 13. dll ranges dll range min max unit slow 40 100 msps fast 80 250 msps
isla224s 28 fn7911.1 may 7, 2012 isla214s35), and for any other pr oduct configuration that uses clkdiv > 1. in both states, the setup and hold times with respect to the sample clock remain the same. contact the factory for more details. address 0xb6: calibration status the lsb at address 0xb6 can be read to determine calibration status. the bit is ?0? during calibration and goes to a logic ?1? when calibration is complete.this register is unique in that it can be read after por at calibration, unlike the other registers on chip, which can?t be read until calibration is complete. device test the device can produce preset or user defined patterns on the digital outputs to facilitate in-sit u testing. a user can pick from preset built-in patterns by writin g to the output test mode field [7:4] at 0xc0 or user defined patterns by writing to the user test mode field [2:0] at 0xc0. the user defined patterns should be loaded at address space 0xc1 through 0xd0, see the ?spi memory map? on page 31 for more detail. the test mode is enabled asynchronously to the sample clock, therefore several sample clock cycles may elapse before the data is present on the output bus. address 0xc0: test_io bits 7:4 output test mode these bits set the test mode acco rding to the description in ?spi memory map? on page 31. bits 2:0 user test mode the three lsbs in this register determine the test pattern in combination with registers 0xc1 through 0xd0. refer to the ?spi memory map? on page 31. address 0xc1: user_patt1_lsb address 0xc2: user_patt1_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 1. address 0xc3: user_patt2_lsb address 0xc4: user_patt2_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 2 address 0xc5: user_patt3_lsb address 0xc6: user_patt3_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 3. address 0xc7: user_patt4_lsb address 0xc8: user_patt4_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 4. address 0xc9: user_patt5_lsb address 0xca: user_patt5_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 5. address 0xcb: user_patt6_lsb address 0xcc: user_patt6_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 6. address 0xcd: user_patt7_lsb address 0xce: user_patt7_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 7. address 0xcf: user_patt8_lsb address 0xd0: user_patt8_msb these registers define the lower and upper eight bits, respectively, of the user-defined pattern 8. address 0xdf - 0xf3: jesd204 registers address 0xdf-0xee: jesd204 parameter interface this set of registers controls the jesd204 transmitter configuration. by programming these parameters, the system can select between efficient an d simple packing, select the number of powered up serdes lanes, choose the adc resolution transmitted, and so on. the jesd204 parameters for standard dual channel products are shown in table 5. this is a small subset of the total number of co nfigurations supported; contact the factory for details. 0xe0 through 0xed are the jesd 204 parameter registers. these parameters are written to set the transport layer mapping of the jesd204 transmitter in this product family. these registers can be written to shift between efficient and simple packing, to enable or bypass scrambling, an d to reduce the number of powered up lanes used in the link. each speed graded product allows downgrading of the jesd204 link (such as reducing the number of lanes, reducing the co nverter resolution, etc), but not upgrading. these parameters are communicated on every lane of the link during the 2nd multi-frame of the initial lane alignment sequence, and therefore can be used by a generic jesd204 receiver the supports th e given configuration. see the jesd204 specification for additional information on how these registers are used in a jesd204 system, including encoding rules. address 0xdf: jesd204_update_config_start bit 0 update_start this self-resetting bit is used to indicate that some or all the jesd204 parameters (addresses 0xe0 through 0xed) are going to be written. writing a ?1? to this bit will hold the jesd204 pll and transmitter in a reset stat e while these parameters are written, because these parameters can affect the transmitter?s
isla224s 29 fn7911.1 may 7, 2012 dynamic behavior (such as modifying the pll?s frequency multiplication). the bit will automatically reset to a ?0? once a ?1? is written to address 0xee bit[ 0] ?update_config w1tc?. the recommended sequence for modifying the jesd204 transmitter is numbered as follows: 1. write a ?1? to 0xdf bit[0] 2. write some or all modified values to 0xe0 through 0xec 3. write a ?1? to 0xee bit[0]. note: 0xdf bit[0] and 0xee bit[0] will automatically be reset to a ?0? once configuration has been applied to the circuitry. address 0xe0: jesd204_config_0 bits 7:0 ?did?, jesd204 device id number. address 0xe1: jesd204_config_1 bits 3:0 ?bid?, jesd204 bank id. address 0xe2: jesd204_config_2 bits 4:0 ?lid? jesd204 lane id. address 0xe3: jesd204_config_3 bit 7 ?scr?, jesd204 scr controls if scrambling across the serdes lane(s) is enabled (?1? means enabled). bits 4:0 ?l?, jesd204 l is the number of serdes lanes in the link. address 0xe4: jesd204_config_4 bits 7:0 ?f?, jesd204 number of octets per frame period. address 0xe5: jesd204_config_5 bits 4:0 ?k? jesd204 number of frame periods per multi-frame period. this product family supports the full programmable range of k (decimal 0 through 31), although note that the jesd204 standard dictates a minimum number for this parameter that is configuration dependent. address 0xe6: jesd204_config_6 bits 7:0 ?m? jesd204 number of converters per device. address 0xe7: jesd204_config_7 bits 7:6 ?cs?, jesd204 cs is the number of control bits per sample (always ?0? for this product family). bits 4:0 ?n?, jesd204 n is the converter resolution. address 0xe8: jesd204_config_8 bits 4:0 ?n??, jesd204 n? is the total number of bits per sample. address 0xe9: jesd204_config_9 bits 4:0 ?s?, jesd204 number of samples per converter per frame cycle. address 0xea: jesd204_config_10 bit 7 ?hd?, jesd204 hd indicates if a converter?s sample can be split across multiple lanes in the link (always ?0? for this product family). bits 4:0 ?cf?, jesd204 cf is the number of control fames per frame clock (always ?0? for this product family). address 0xeb: jesd204_config_11 bits 7:0 ?res1?, jesd204 reserved for future use. address 0xec: jesd204_config_12 bits 7:0 ?res2?, jesd204 reserved for future use. address 0xed: jesd204_config_13 bits 7:0 ?fchk? jesd204 checksum (unsigned sum mod 256) of all the other jesd204 parameter register values. this is a read-only register, as the checksum is calculated by the device. address 0xee: jesd204_update_config_complete bit 0 update_complete this self-resetting bit is used to indicate that all the modifications to the jesd204 parameters are complete. address 0xef: jesd204_pll_monitor_reset bit 0 ?pll_lock_mon_rst?, this self resetting register resets the state of the 0xf0 bit[0] ?latched_pll_lockn? bit. the purpose of this pair of bits is as a debugging feature to the system designer. the ?latched_pll_lockn? bit indicates if the jesd204 transmitter pll inside the device has at any ti me lost lock since the last ?1? was written to the ?pll_lock_mon_rst? bit. this can be used to help identify the source of intermittent link lost errors in the system. address 0xf0: jesd204_status bit 2 ?op_cfg_wrong? indicates if the jesd204 parameters (registers 0xe0 through 0xed) are supported by the jesd204 transmitter (a ?1? indicates they are not supported, a ?0? indicates they are supported). bit 1 ?pll_lockn? indicates if the jesd204 transmitter pll is currently locked (a ?1? indicates it is not locked, a ?0? indicates it is locked). bit 0 ?latched_pll_lockn? indicate s if the jesd 204 transmitter pll has lost lock since the last assertion of the ?pll_lock_mon_rst? (see register 0xef description for more information). address 0xf1: jesd204_sync bit 0 ?sync_req? this register provides a spi-programmable interface that can be used to assert and de-assert the jesd204 sync~ functionality. certain systems may benefit from the elimination of sync~ as a separate board-level lvds signal (and the power, pcb space, and pins it consumes), and these systems can use this register to functionally assert and de-assert sync~. for this bit to have any effect, a ?1? must have previously been written to the sync_function (address 0x77, bit 0). a ?1? written to this bit will result in behavior identical to the assertion of sync~ (comma char acter generation), and ?0? will result in the behavior identical to the de-assertion of sync~ (initial lane alignment sequence followed by converter data). usage of this spi sync~ capability may compromise the system?s ability to perform multi- chip time alignment, as the sync~ asserted to de-asserted tran sition using this register is not well timed with respect to sample clock.
isla224s 30 fn7911.1 may 7, 2012 address 0xf2: jesd204_trans_pat_config bit 0 ?no_mf_lane_sync?, by default, this device family assumes that both sides of the link support lane synchronization. as per the jesd204 rev a standard, in this case continuous frame alignment monitoring via character substitution (section 5.3.3.4) is modified such that a differen t control character is substituted when the octet reoccurrence happens at the end of a multi- frame. this behavior occurs when bit 0 is ?0? (the power on default). writing a ?1? to bit 0 will inform the je sd204 transmitter than the receiving device does no t support lane synchronization, and therefore the transmitter will no longer substitute this different control character when reoccurrence of octets occurs at the end of a multi-frame. bit 1 ?trans_pat_max_len? there is so me ambiguity of the proper length of the jesd204 rev a section 5.1.6.2 required transport layer test pattern. specifically, that the description perhaps should have ?max()? in place of ?min()? for the equation defining the length of the pattern. setting bit 1 in this register to a ?0? (also the power-on default) and issuing this test pattern by writing to 0xc0 will cause the pattern to assume a ?min()? interpretation of the pattern described in section 5.1.6.2. setting the bit to a ?1? will assume a ?max()? interpretation of the described pattern. address 0xf3: jesd204_cml_polarity 0xf3 bit[2:0]: ?tx polarity flip lane x? this register allows the system designer to invert the sense of the serdes pins on a per lane basis. for example, writing a ?1? to bit[0] causes lane0n to functionally become lane0p an d lane0p to become lane0n. this feature allows the system designer to avoid having to crossover p and n sides of the cml pair on the board to match pin out and layout of the transm itter and receiver. typically, a trace crossover would require vias, which can degrade the signal integrity of the high-speed serdes lanes. address 0xfe: offset/gain_adjust_enable bit 0 at this register must be se t high to enable adjustment of offset coarse and fine adjustme nts corea (0x20 and 0x21), coreb (0x26 and 0x27) and gain medium and gain fine adjustments corea (0x23 and 0x24), coreb (0x29 and 0x2a). it is recommended that new data be written to the offset and gain adjustment registers corea(0x20, 0x21, 0x23, 0x24) and coreb(0x26, 0x27, 0x29, 0x2a) while bit 0 is a ?0?. subsequently, bit 0 should be set to ?1? to allow the values written to the aforementioned registers to be used by the adc. bit 0 should be set to a ?0? upon completion.
isla224s 31 fn7911.1 may 7, 2012 spi memory map addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex) spi config/control 00 port_config sdo active lsb first soft reset mirror (bit5) mirror (bit6) mirror (bit7) 00h 01 reserved reserved 02 burst_end burst end address [7:0] 00h 03-07 reserved reserved dut info 08 chip_id chip id # read only 09 chip_version chip version # read only 0a-0f reserved reserved device config/control 10-1f reserved reserved 20 offset_coarse_corea coarse offset cal. value 21 offset_fine_corea fine offset cal. value 22 gain_coarse_corea reserved coarse gain cal. value 23 gain_medium_corea medium gain cal. value 24 gain_fine_corea fine gain cal. value 25 modes_corea reserved power down mode corea [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not reset by soft reset 26 offset_coarse_coreb coarse offset cal. value 27 offset_fine_coreb fine offset cal. value 28 gain_coarse_coreb reserved coarse gain cal. value 29 gain_medium_coreb medium gain cal. value 2a gain_fine_coreb fine gain cal. value 2b modes_coreb reserved power down mode coreb [2:0] 000 = pin control 001 = normal operation 010 = nap 100 = sleep other codes = reserved 00h not reset by soft reset 2c-6f reserved reserved 70 skew_diff differential skew 80h 71 phase_slip reserved next clock edge 00h 72 clock_divide clock divide [2:0] 000 = pin control 001 = divide by 1 010 = divide by 2 100 = divide by 4 other codes = reserved 00h not reset by soft reset
isla224s 32 fn7911.1 may 7, 2012 device config/control 73 output_mode_a output format [2:0] 000 = two?s complement (default) 010 = gray code 100 = offset binary other codes = reserved 00h not reset by soft reset 74 output_mode_b dll range 0 = fast 1 = slow default=?0 ? 00h not reset by soft reset 75-76 reserved reserved 77 sync_function clkdivrst 78-b5 reserved reserved b6 cal_status reserved calibration done read only b7-bf reserved spi memory map (continued) addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex)
isla224s 33 fn7911.1 may 7, 2012 device test c0 test_io output test mode [7:4] jesd test user test mode [2:0] user test mode (single adc products only) 0 = user pattern 1 only 1 = cycle pattern 1 through 2 2 = cycle pattern 1 through 3 3 = cycle pattern 1 through 4 4 = cycle pattern 1 through 5 5 = cycle pattern 1 through 6 6 = cycle pattern 1 through 7 7 = cycle pattern 1 through 8 user test mode (dual and interleaved adc products only) 0 = cycle pattern 1 through 2 1 = cycle pattern 1 through 4 2 = cycle pattern 1 through 6 3 = cycle pattern 1 through 8 4 -7 = na 00h <7:4>=output test, <3> = jesd test jesd test=0 output test = 0x0= output test mode off. during calibration msb justified constant output 0xcccc 0x1 = midscale adjust ed by numeric format 0x2 = plus full scale, ad justed by numeric format 0x3 = minus full scale adjusted by numeric format 0x4 = checkboard output - 0xaaaa, 0x5555 0x5 = reserved 0x6 = reserved 0x7 = 0xffff, 0x0000 all on pattern 0x8 = user pattern 8 deep, msb justified with output 0x9 = reserved 0xa, count-up ramp 0xb, prbs-9 0xc, prbs-15 0xd, prbs-23 0xe, prbs-31 0xf = reserved jesd test=1 output test = 0x0 =link layer repeat k28.5+lane alignment sequence 0x1, link layer repeat k28.5 0x2, link layer repeat d21.5 0x3, link layer repeat k28.7 0x4, link layer prbs-7 0x5, link layer prbs-23 0x6, link layer all zeros 0x7, link layer all ones 0x8-0xe, reserved 0xf, jesd204 section 5.1.6.2 transport layer test pattern c1 user_patt1_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c2 user_patt1_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c3 user_patt2_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c4 user_patt2_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c5 user_patt3_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c6 user_patt3_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c7 user_patt4_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h c8 user_patt4_msb b15 b14 b13 b12 b11 b10 b9 b8 00h c9 user_patt5_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h ca user_patt5_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cb user_patt6_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h cc user_patt6_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cd user_patt7_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h ce user_patt7_msb b15 b14 b13 b12 b11 b10 b9 b8 00h cf user_patt8_lsb b7 b6 b5 b4 b3 b2 b1 b0 00h d0 user_patt8_msb b15 b14 b13 b12 b11 b10 b9 b8 00h d1-de reserved reserved spi memory map (continued) addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex)
isla224s 34 fn7911.1 may 7, 2012 jesd204 interface df jesd204_update_config_star t update_ start 00h e0 jesd204_config_0 did (device id number) 00h e1 jesd204_config_1 bid (bank id number) see description for default settings e2 jesd204_config_2 lid (lane id number) e3 jesd204_config_3 scr l (number of lanes per device) e4 jesd204_config_4 f (number of octets per frame) e5 jesd204_config_5 k (number of frames per multi-frame) e6 jesd204_config_6 m (number of converters per device) e7 jesd204_config_7 cs (number of control bits per sample) n (converter resolution in bits) e8 jesd204_config_8 n? (total number of bits per sample) e9 jesd204_config_9 s (number of samples per converter per frame) ea jesd204_config_10 hd cf (number of control words per frame per link) eb jesd204_config_11 res1 ec jesd204_config_12 res2 ed jesd204_config_13 fchk (checksum) ee jesd204_update_config_com plete update_ complete 00h ef jesd204_pll_monitor_reset pll_lock_ mon_rst 00h f0 jesd204_status op_confg_ wrong pll_lockn latched_ pll_lockn 00h f1 jesd204_sync sync_req f2 jesd204_trans_pat_config trans_pat_ max_len no_mf_ lane_sync f3 jesd204_cml_polarity lane_2_ polarity lane_1_ polarity lane_0_ polarity 00h f4-fd reserved reserved fe offset/gain_adjust_enable enable ?1?=enable 00h ff reserved reserved spi memory map (continued) addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) def. value (hex)
isla224s 35 fn7911.1 may 7, 2012 equivalent circuits figure 58. analog inputs figure 59. clock inputs figure 60. tri-level digital inputs figure 61. digital inputs figure 62. cml outputs figure 63. vcm_out output avdd inp inn avdd csamp 4pf csamp 4pf to charge pipeline to charge pipeline e1 e3 e3 e2 e2 e1 600 avdd clkp clkn avdd avdd to clock-phase generation avdd 11k 18k 11k 18k avdd input avdd avdd avdd to sense logic 75k 75k 75k 75k 280 input ovdd ovdd 280 to logic 20k ovdd (20k pull-up on resetn only) lane[2:0]p ovdd ovdd 16ma data data lane[2:0]n ovdd 50 50 vcm avdd 1.0v + ?
isla224s 36 fn7911.1 may 7, 2012 adc evaluation platform intersil offers adc evaluation platforms which can be used to evaluate any of intersil?s high speed adc products. each platform consists of a fpga based data capture motherboard and a family of adc daughtercards. the usb interface and evaluation platform control software allow a user to quickly evaluate the adc?s performance at a user?s specific application frequency requirements. more information is available at http://www.intersil.com/converters/adc_eval_platform/ layout considerations split ground and power planes data converters operating at high sampling frequencies require extra care in pc board layout. many complex board designs benefit from isolating the analog and digital sections. analog supply and ground planes should be laid out under signal and clock inputs. locate the digital planes under outputs and logic pins. grounds should be joined under the chip. clock input considerations use matched transmission lines to the transformer inputs for the analog input and clock signals. locate transformers and terminations as close to the chip as possible. exposed paddle the exposed paddle must be electrically connected to analog ground (avss) and should be connected to a large copper plane using numerous vias for op timal thermal performance. bypass and filtering bulk capacitors should have lo w equivalent series resistance. tantalum is a good choice. for best performance, keep ceramic bypass capacitors very close to device pins, as longer traces between the ceramic bypass capacitors and the device pins will increase inductance, which can result in diminished dynamic performance. best practices bypassi ng is especially important on the avdd and ovdd(pll) power supply pins. whenever possible, each supply pin should have its own 0.1uf bypass capacitor. make sure that connections to ground are direct and low impedance. avoid forming ground loops. cml outputs output traces and connections must be designed for 50 (100 differential) characteristic impe dance. keep traces direct and short, and minimize bends and vias where possible. avoid crossing ground and power-plane br eaks with signal traces. keep good clearance (at least 5 trace widths) between the serdes traces and other signals. given the speed of these outputs and importance of maintaining an open eye to achieve low ber, signal integrity simulations are recommended, especially when the data lane rate exceeds 3g bps and/or the trace or cable length between the adc and the re ciever gets larger than 20cm. unused inputs standard logic inputs (resetn, csb, sclk, sdio, sdo) which will not be operated do not require connection to ensure optimal adc performance. these inputs can be left floating if they are not used. tri-level inputs (napslp) accept a floating input as a valid state, and therefore should be biased according to the desired functionality. definitions analog input bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by fft analysis) is reduced by 3db from its full-scale low-frequency value. this is also referred to as full power bandwidth. aperture delay or sampling delay is the time required after the rise of the clock input for the sa mpling switch to open, at which time the signal is held for conversion. aperture jitter is the rms variation in aperture delay for a set of samples. clock duty cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. differential non-linearity (dnl) is the deviation of any code width from an ideal 1 lsb step. effective number of bits (enob) is an alternate method of specifying signal to noise-and-dist ortion ratio (sinad). in db, it is calculated as: enob = (sinad - 1.76)/6.02 gain error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage less than 2 lsb. it is typically expressed in percent. i2e the intersil interleave engine. this highly configurable circuitry performs estimates of offset, gain, and sample time skew mismatches between the core converters, and updates analog adjustments for each to minimize interleave spurs. integral non-linearity (inl) is the maximum deviation of the adc?s transfer function from a best fit line determined by a least squares curve fit of that transfer function, measured in units of lsbs. least significant bit (lsb) is the bit that has the smallest value or weight in a digital word. its value in terms of input voltage is v fs /(2 n - 1) where n is the resolution in bits. missing codes are output codes that ar e skipped and will never appear at the adc output. these codes cannot be reached with any input value. most significant bit (msb) is the bit that has the largest value or weight. pipeline delay is the number of clock cycles between the initiation of a conversion and th e appearance at the output pins of the data. power supply rejection ratio (psrr) is the ratio of the observed magnitude of a spur in the adc fft, caused by an ac signal superimposed on the power supply voltage. signal to noise-and-distortion (sinad) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one half the clock frequency, including harmonics but excluding dc.
isla224s 37 fn7911.1 may 7, 2012 signal-to-noise ratio (without harmonics) is the ratio of the rms signal amplitude to the rms sum of all other spectral components below one-half the sampling frequency, excluding harmonics and dc. snr and sinad are either given in units of db when the power of the fundamental is used as the reference, or dbfs (db to full scale) when the converter?s full-scale input power is used as the reference. spurious-free-dynamic range (sfdr) is the ratio of the rms signal amplitude to the rms value of the largest spurious spectral component. the largest spurious spectral component may or may not be a harmonic.
isla224s 38 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7911.1 may 7, 2012 for additional products, see www.intersil.com/product_tree intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isla224s12 , isla224s20 , isla224s25 . to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change april 17, 2012 release of 125msps grade; page 1 - key specifications changes showing snr/sfdr page 1 bullets at 30m hz and 190mhz (was 30mhz and 363mhz) pin-compatible family updated by removing model isla224s17 page 3 - updated ordering information table by remo ving part isla224s17ir1z, removing "coming soon" from part isla224s12ir1z and addi ng eval board "ISLA224S25IR48EV1Z" page 5 - updated electrical specs as follows: added min and max values to isla224s12 full-scale analog input range, input offset voltage, 1.8v analog and digi tal supply voltage and added max values to 1.8 analog and digital supply current page 6 to page 7 added max values to isla224s12 total power dissipation normal mode, nap mode and sleep mode added min and max values to isla224s12 differential nonlinearity and changed typ from 0.3 to 0.18 changed typ in integral nonlinearity from 2.3 to 2.0 added conditions to minimum conversion rate and added typical value to isla224s12 added minimum and maximum serdes lane data rate specs added min values for isla224s12 fin = 105mhz for sign al to noise ratio, signal to noise and distortion, effective number of bits and spurious-free dynamic range page 10 - typical performance curves changes added to figure 9 - power vs fsample 2 lanes and efficient packing added differential and integral nonlinearity, noise hi stogram and single tone spectrum graphics for 125 mbps page 22 - updated jesd204 configurations and clock frequencies table page 22 - rewrote lane data rate section page 23 - updated jes204 parameters table by removing product column page 26 - updated table heads for tables 7, 8 and 9 page 31 - updated spi memory map december 20, 2011 fn7911.0 initial release
isla224s 39 fn7911.1 may 7, 2012 package outline drawing l48.7x7g 48 lead quad flat no-lead plastic package rev 0, 1/10 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 7.00 b a 7.00 (4x) 0.15 index area pin 1 pin #1 44x 0.50 4x 5.5 48 37 exp. dap 1 36 25 48x 0.40 4 13 24 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. c 1.00 max see detail "x" c c 0.08 seating plane c 0.10 6 6 6 .80 sq 5.70 sq ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 20 ) 48x 0.20 5.70 sq. index area

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